The disclosed embodiments of the present invention relate to accessing buffered data (e.g., cached data), and more particularly, to a storage system having data storage lines (e.g., cache lines) with different data storage line sizes (e.g., different cache line sizes).
Cache memories are high speed buffers used to temporarily hold, for repeated access, portions of the contents of a larger and slower memory such as a main memory. Most modern caches are organized as a set of entries. Each entry consists of a block (or line) of data, and an address tag; the address tag is associated with the location of the data in the larger main memory. The cache is accessed associatively—the key to the cache is not the location in the cache but the location in the main memory. To accelerate access, of course, the cache may not be fully associative, but rather may be set associative, direct mapped or hashed. Most of caches include cache lines each having a fixed cache line size. In a slightly more complex design, a sector cache is used. A sector cache is organized as a set of sectors, and there is an address tag associated with each sector. The sector itself is divided into subsectors. Each subsector has a valid bit, and thus only some of the subsectors of a sector need to be present. When there is a cache miss to a sector, a resident sector is evicted, an address tag is set to the address of the new sector, and a single subsector is fetched. When there is a cache miss to a subsector, but the sector containing it is already present in the cache, only that needed subsector is fetched.
The original reason for the sector cache is that the discrete transistor logic of the time makes a sector design easier to build than the currently more common non-sectored design with the unit of data transfer and addressing as either a “block” or a “line”. In a normal, non-sectored cache, the only way to have a very large cache capacity with a relatively small number of tag bits is to make the cache blocks (lines) very large. However, the problem in this case is that every cache miss requires a large block be fetched in its entirety. With a sector cache, it is possible to fetch only a portion of a block (or sector), and thus the time to handle a cache miss, and the bus traffic, can both be significantly reduced. Thus, although it is likely that sector caches will have higher cache miss ratios than normal caches, there is the possibility that when timing is considered, the sector cache will be found to have better performance. However, the problem with the sector design is that a sector would typically be evicted from the cache before all of its subsectors are loaded with data, and thus a large fraction of the cache capacity would be unused. Specifically, sector caches have the feature that large numbers of bytes can be tagged using relatively small numbers of tag bits, while still only transferring small blocks when a miss occurs. However, one tag would correspond to a large numbers of bytes. When the cache line is replaced very often, the rest of bytes might still be empty. It may consume precious space of the cache memory.